Logic Family Research Articles

NbN-based half-flux-quantum element for integration with superconducting qubits

Half-flux-quantum (HFQ) logic is a superconductor logic family comprising conventional Josephson junctions (0-JJs) and π Josephson junctions (π-JJs). The energy scale of HFQ logic can be flexibly reduced by phase shifts owing to π-JJs; thus, HFQ circuits are a promising building block for qubit interface circuits. In this study, we demonstrate an NbN-based HFQ circuit element compatible with NbN-based superconducting qubits for all-NbN monolithic integration of qubits and HFQ circuits. The use of NbN is beneficial for both qubits and HFQ circuits owing to its high-quality junctions and high kinetic inductance. First, we developed a prototype of an NbN-based 0-JJ/π-JJ hybrid fabrication process for designing HFQ circuits. We evaluated 0-JJs and π-JJs fabricated through the hybrid process, which demonstrated that the 0-JJs had a small deviation with regard to critical current density and the π-JJs had a sufficiently high critical current density to work as π phase shifters. Furthermore, we fabricated an HFQ superconducting quantum interference device, which is one of the most fundamental elements in HFQ circuits, and observed clear HFQ-period modulation in the magnetic flux dependence of the maximum current at 4.2 K.

Sequent Calculi for Choice Logics

Choice logics constitute a family of propositional logics and are used for the representation of preferences, with especially qualitative choice logic (QCL) being an established formalism with numerous applications in artificial intelligence. While computational properties and applications of choice logics have been studied in the literature, only few results are known about the proof-theoretic aspects of their use. We propose a sound and complete sequent calculus for preferred model entailment in QCL, where a formula F is entailed by a QCL-theory T if F is true in all preferred models of T. The calculus is based on labeled sequent and refutation calculi, and can be easily adapted for different purposes. For instance, using the calculus as a cornerstone, calculi for other choice logics such as conjunctive choice logic (CCL) and lexicographic choice logic (LCL) can be obtained in a straightforward way.

Design method for unbalanced ternary logic family based on binary memristors

Design method for unbalanced ternary logic family based on binary memristors

Design of a Power Efficient Model of PWM Generator for Green Communication using High Performance FPGAs

Aim: This paper will focus on promoting the ideas of green communication Background: Pulse Width Modulation (PWM) generator is used to control the power transfer in any communication model. It is one of the most crucial parts of an electrical circuit. Our main focus in this research work is to develop an energy and power-efficient PWM generator by using Field Programmable Gate Array (FPGA) logic to elevate green communication Objective: Our main focus in this research work is to develop an energy and power-efficient PWM generator by using Field Programmable Gate Array (FPGA) logic to elevate green communication. Methods: In order to make the PWM suitable for GC, we have implemented the design on VIVADO ISE from Xilinx. The power analysis as well as resource utilization are targeted on three different FPGAs. Results: Different IO standards of Stub Series Terminated Logic (SSTL) family are explored at different FPGA’s. Power analysis is deployed on the 7 series FPGAs of 3 different categories i.e., Spartan 7 (channel length = 28 nm), Kintex 7 (channel length = 20 nm) and ultra scale Zynq 7 (channel length = 16 nm). Conclusion: It can be concluded from power analysis that SPARTAN-7 device is the most powerefficient and ZYNQ Ultra scale+utilizes the highest amount of power. However, KINTEX-7 Ultrascale device lies in the middle of both these devices as far as power consumption is concerned. There is a reduction of 43.07% TP consumption for SPARTAN-7 device with SSTL135 IO when equated with ZYNQ Ultra scale+ with SSTL18_I IO. Also, it can be observed from sections 5.1, 5.2 and 5.3 that there is more contribution of DP in TP consumption than SP. Hence the device utilizes additional power when it is in active state than static state. Since PWM generator is an integral part of data and wireless communication, it should require less power for proficient transmission and wellorganized green computing and communication.

High-density superconductive logic circuits utilizing 0 and π josephson junctions

Superconductor Electronics (SCE) is a fast and power-efficient technology with great potential for overcoming conventional CMOS electronics’ scaling limits. Nevertheless, the primary challenge confronting SCE today is its integration level, which lags several orders of magnitude behind CMOS circuits. In this study, we have innovated and simulated a novel logic family grounded in the principles of phase shifts occurring in 0 and π Josephson junctions. The fast phase logic (FPL) eliminates the need for large inductor loops and shunt resistances by combining the half-flux and phase logic. Therefore, the Josephson junction (JJ) area only limits the integration density. The cells designed with this paradigm are fast, and the clock-to-Q delay for logic cells is about 4ps. While maintaining over 50% parameter margins for wiring cells. This logic is power efficient and can increase the integration by at least 100×in the SCE chips.

Angell and McCall Meet Wansing

In this paper, we introduce a new logic, which we call AM3. It is a connexive logic that has several interesting properties, among them being strongly connexive and validating the Converse Boethius Thesis. These two properties are rather characteristic of the difference between, on the one hand, Angell and McCall’s CC1 and, on the other, Wansing’s C. We will show that in other aspects, as well, AM3 combines what are, arguably, the strengths of both CC1 and C. It also allows us an interesting look at how connexivity and the intuitionistic understanding of negation relate to each other. However, some problems remain, and we end by pointing to a large family of weaker logics that AM3 invites us to further explore.

Voltage-controlled cryogenic Boolean logic gates based on ferroelectric SQUID and heater cryotron

The recent progress in quantum computing and space exploration led to a surge in interest in cryogenic electronics. Superconducting devices such as Josephson junction, Josephson field effect transistor, cryotron, and superconducting quantum interference device (SQUID) are traditionally used to build cryogenic logic gates. However, due to the superconducting nature, gate-voltage-based control of these devices is extremely difficult. Even more challenging is to cascade the logic gates because most of these devices require current bias for their operation. Therefore, these devices are not as convenient as the semiconducting transistors to design logic gates. Here, to overcome these challenges, we propose a ferroelectric SQUID (FeSQUID) based voltage-controlled logic gates. FeSQUID exhibits two different critical current levels for two different voltage-switchable polarization states of the ferroelectric. We utilize the polarization-dependent (hence, voltage-controllable) superconducting to resistive switching of FeSQUID to design Boolean logic gates such as Copy, NOT, AND, and OR gates. The operations of these gates are verified using a Verilog-A-based compact model of FeSQUID. Finally, to demonstrate the fanning out capability of FeSQUID-based logic family, we simulate a two-input XOR gate using FeSQUID-based NOT, AND, and OR gates. Together with the ongoing progress on FeSQUID-based non-volatile memory, our designed FeSQUID-based logic family will enable all FeSQUID-based cryogenic computer, ensuring minimum mismatch between logic and memory blocks in terms of speed, power consumption, and fabrication process.

Some Logics in the Vicinity of Interpretability Logics

In this paper we shall define semantically some families of propositional modal logics related to the interpretability logic \(\mathbf{IL}\). We will introduce the logics \(\mathbf{BIL}\) and \(\mathbf{BIL}^{+}\) in the propositional language with a modal operator \(\square\) and a binary operator \(\Rightarrow\) such that \(\mathbf{BIL}\subseteq\mathbf{BIL}^{+}\subseteq\mathbf{IL}\). The logic \(\mathbf{BIL}\) is generated by the relational structures \(\left<X,R,N\right>\), called basic frames, where \(\left<X,R\right>\) is a Kripke frame and \(\left<X,N\right>\) is a neighborhood frame. We will prove that the logic \(\mathbf{BIL}^{+}\) is generated by the basic frames where the binary relation \(R\) is definable by the neighborhood relation \(N\) and, therefore, the neighborhood semantics is suitable to study the logic \(\mathbf{BIL}^{+}\) and its extensions. We shall also study some axiomatic extensions of \(\mathsf{\mathbf{BIL}}\) and we will prove that these extensions are sound and complete with respect to a certain classes of basic frames.

A Generalization of Beall’s Off-Topic Interpretation

AbstractIn one of his papers, JC Beall advanced a new and interesting interpretation of Weak Kleene logic, in terms of on-topic/off-topic. In brief, Beall suggests to read the third value as off-topic, whereas the two classical values are read as true and on-topic and false and on-topic. Building on Beall’s new interpretation, the aim of this paper is threefold. First, we discuss two motivations to enrich Beall’s interpretation, and offer an alternative semantic framework that reflects our motivations. Second, by making use of our new framework, we will offer a new interpretation of the logic of Catuskoti which combines Beall’s proposal of having FDE as the correct logic with the on-topic/off-topic divide. Finally, we will offer a general result that will allow us to make sense of a family of infectious logics in terms of Beall’s on-topic/off-topic reading.

High-performance LFSR circuit design based on XOR gates

The research discussed in this article is focused on analysing the effects of XOR gates based on different logic families, namely MOS Current Mode Logic (MCML), dynamic current logic, and PTL, on the performance of linear feedback shift register (LFSR) circuits. The aim of the study is to evaluate the power dissipation and critical path latency of the circuits while comparing the results with earlier works in the field. To achieve this, the researchers implemented the 3, 4, and 5-bit LFSR circuits using Verilog HDL code and synthesized them on the Cadence tool using 90nm CMOS technology. The study concludes that LFSR circuits based on XOR gates outperform previous LFSR circuits in terms of power dissipation. The research also offers a comparative analysis of the different types of XOR gates used in the LFSR circuits, highlighting the advantages and disadvantages of each type. The results of the study can be useful for researchers working in the field of circuit design, as well as for practitioners who are interested in developing low-power and efficient LFSR circuits.

Polyhedral semantics and the tractable approximation of Łukasiewicz infinitely-valued logic

Abstract In this work, we present polyhedral semantics as a means to tractably approximate Łukasiewicz infinitely-valued logic (Ł$_{\infty}$). As Ł$_{\infty}$ is an expressive multivalued propositional logic whose decision problem is NP-complete, we show how to to obtain an approximation for this problem providing a family of multivalued logics over the same language as Ł$_{\infty}$. Each element of the family is associated to a polynomial-time linear program, thus providing a tractable way of deciding each intermediate step. We also investigate properties of the logic system derived from polyhedral semantics and the details of an algorithm for the approximation process.

Semantical investigations on non-classical logics with recovery operators: negation

Abstract We investigate mathematical structures that provide natural semantics for families of (quantified) non-classical logics featuring special unary connectives, known as recovery operators, that allow us to ‘recover’ the properties of classical logic in a controlled manner. These structures are known as topological Boolean algebras, which are Boolean algebras extended with additional operations subject to specific conditions of a topological nature. In this study, we focus on the paradigmatic case of negation. We demonstrate how these algebras are well-suited to provide a semantics for some families of paraconsistent Logics of Formal Inconsistency and paracomplete Logics of Formal Undeterminedness. These logics feature recovery operators used to earmark propositions that behave ‘classically’ when interacting with non-classical negations. Unlike traditional semantical investigations, which are carried out in natural language (extended with mathematical shorthand), our formal meta-language is a system of higher-order logic (HOL) for which automated reasoning tools exist. In our approach, topological Boolean algebras are encoded as algebras of sets via their Stone-type representation. We use our higher-order meta-logic to define and interrelate several transformations on unary set operations, which naturally give rise to a topological cube of opposition. Additionally, our approach enables a uniform characterization of propositional, first-order and higher-order quantification, including restrictions to constant and varying domains. With this work, we aim to make a case for the utilization of automated theorem proving technology for conducting computer-supported research in non-classical logics. All the results presented in this paper have been formally verified, and in many cases obtained, using the Isabelle/HOL proof assistant.

SFQ/DQFP Interface Circuits

The increasing complexity of hybrid superconductive computing systems has made interface circuits between logic families an issue of growing importance. In this paper, interface circuits between single flux quantum (SFQ) and directly coupled quantum flux parametron (DQFP) logic families to achieve high speed, low power hybrid superconductive computing systems are presented. In the proposed DQFP-to-SFQ interface, margins greater than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\pm$</tex-math></inline-formula> 20% for the critical current of the JJs, bias currents, and inductances are exhibited. The margins of the excitation current of the DQFP buffer are -38% and +35% with the frequency of the excitation current in the range of 2 GHz to 10 GHz. In the proposed SFQ-to-DQFP interface, the margins are greater than -33% and +25%. The margins of the excitation current of the DQFP buffer are -50% and +20% for frequencies ranging from 2 GHz to 10 GHz. Since no transformers are required, the physical area of the adiabatic portion of the interface circuits is significantly less than existing interface circuits. The SFQ-to-DQFP interface circuit operates at frequencies approaching 20 GHz. These interface circuits therefore exhibit high parameter margins and operating frequencies while requiring significantly less area as compared to existing interface circuits. The proposed interface circuits support the use of both ultra-low power and high speed logic families in complex hybrid superconductive systems.

Adopting a Standard Track Routing Architecture for Next-Generation Hybrid AC/DC-Biased Logic Circuits

The adiabatic quantum-flux-parametron (AQFP) and rapid single flux quantum (RSFQ) logic families both provide distinct advantages for data processing using superconductor electronics. The development of next-generation AQFP-RSFQ hybrid logic circuits provides the opportunity to combine the benefits of both of these logic families. Adopting a standard track routing architecture for both AQFP and RSFQ layouts provides a unified framework for physical layout synthesis. We demonstrate a standard track routing architecture developed under the ColdFlux project and its implementation within AQFP. An additional advantage of the standard track routing architecture is that it provides a systematic way to overcome metal density requirements for modern-day fabrication processes. It also provides a methodical approach towards strategic moat placement for protection against unwanted flux trapping. Implementations of passive transmission line (PTL) connections and their physical placement for hybrid AQFP-RSFQ circuits are discussed. Several AQFP layouts for the ColdFlux project are redesigned to adopt the standard track routing architecture. Experimental simulation of moat performance is also presented.

A Full-Custom Design Flow and a Top-Down RTL-to-GDS Flow for Adiabatic Quantum-Flux-Parametron Logic Using a Commercial EDA Design Suite

The adiabatic quantum-flux-parametron (AQFP) circuit is a superconductor digital logic family with extremely low power consumption. It consumes five orders less power than the state-of-the-art CMOS circuits and three orders of magnitude less power than RSFQ circuits, another competing digital superconductor technology. The computing resources required by society are increasing every year, and the AQFP circuit is a strong candidate for the next generation of computers. In previous research, a 4-bit MANA microprocessor and a 16-bit Kogge-Stone adder using AQFP logic were designed and demonstrated. These circuits were designed almost by hand, and the development environment needs to be improved to implement AQFP circuits for practical applications. So, we used Synopsys EDA tools typically used for CMOS design to create a full-custom design flow for logic cell design and a top-down flow to design combinational logic circuits automatically. We integrated a circuit design editor with simulation and verification tools for the full-custom design flow. For the top-down flow, we created an environment that automatically performs logic synthesis, path balancing, cell placement, and signal and excitation routing. 1024-bit adders with more than two million Josephson junctions (JJs) have been successfully designed.

All-JJ Logic Based on Bistable JJs

The all-JJ logic family is a promising area and power efficient, scalable single flux quantum (SFQ) technology for application to exascale supercomputers. All-JJ superconductive logic is based on a superconductor-ferromagnet-superconductor (SFS) bistable JJ, enabling nanometer feature sizes in VLSI complexity superconductive systems. In this paper, a mechanical analogy is proposed to describe the dynamic behavior of these bistable JJs. Novel all-JJ logic gates, such as TFF, DFF, OR, AND, and NOT gates, are presented here. All-JJ circuits are composed of bistable JJs, standard JJs, and bias currents, requiring no large inductors within the storage loops. All-JJ logic cells exhibit less delay and power than standard SFQ cells with the same critical current density. All-JJ systems can operate at high frequencies due to the small capacitance of the SFS JJ. A complex all-JJ circuit from the suite of ISCAS'85 benchmark circuits is also characterized. This complex all-JJ circuit exhibits less delay and power as compared to standard SFQ logic. The bias current in a conventional benchmark circuit and all-JJ benchmark circuit is, respectively, 22 mA and 13 mA. The delay of each cell within the conventional benchmark circuit and all-JJ benchmark circuit is, respectively, approximately 20 and 8 ps. A parasitic inductance in series with the JJs disturbs the current distribution within the all-JJ circuits while degrading the margins. To suppress the effects of this parasitic inductance on SFS JJs, small linear inductors are added to manage the current distribution and improve parameter margins.

Two Circuits for Directing and Controlling Ballistic Fluxons

Reversible logic schemes using flux solitons (fluxons) on long Josephson junctions (LJJs) have recently been proposed. The attraction of the fluxon is that it propagates ballistically along an LJJ until it encounters a change in the character of the LJJ, often a designed circuit element. Logic gates involve fluxons interacting with circuit elements and with other fluxons. However, testing of ballistic fluxon circuits requires other circuits outside the logic family to direct and control fluxon motion. We discuss two such <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">non-reversible</i> fluxon control circuits. First, the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">polarity filter gate</i> is a simple non-reversible gate that allows one polarity of fluxon to pass, while reflecting the other polarity. In the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</i> state both polarities reflect. Second, the polarity separator generalizes on the polarity filter concept and allows separation of the two fluxon polarities into different LJJs. We discuss simulations of these structures and possible applications.

An Adiabatic Quantum-Flux-Parametron 8-bit Ripple Carry Adder Using Delay-Line Clocking

Adiabatic quantum-flux-parametron (AQFP) logic is a superconductor logic family that can operate with low switching energy due to adiabatic switching. In a previous study, we proposed a low-latency clocking scheme called delay-line clocking, in which the latency for each logic operation is determined by the propagation delay of the excitation current. We demonstrated several AQFP logic gates with delay-line clocking and demonstrated a phase skipping operation, in which some of the AQFP buffers for phase synchronization are removed to reduce the junction count and energy dissipation. In the present study, we design and demonstrate an AQFP 8-bit ripple carry adder with delay-line clocking to show that delay-line clocking and the phase skipping operation are applicable to large-scale AQFP circuits. The latency of this adder is 960 ps, which is 40% of that for a conventional design. Moreover, due to the phase skipping operation, the junction count is reduced to approximately 70% of that for the conventional design. We find that this adder can operate at up to 4 GHz. The above results indicate that large-scale AQFP circuits can operate with low latency and low junction count by using delay-line clocking and a phase skipping operation.

Optimization and Verification of RSFQ and AQFP Logic Circuits Using JoSIM Tools

Various techniques exist to optimize functioning RSFQ circuits for improved critical margins. Existing techniques generally employ a center of gravity method. We present the additional use of a minimal distance to failure optimization technique through the ad-hoc tools for the superconducting circuit simulation engine JoSIM. These techniques are used to optimize the margins of RSFQ circuits through verification of Josephson junction phase. This verification method is extended to incorporate the output current in an attempt to optimize the highly energy efficient AQFP logic family. Results are presented for pre and post optimized logic circuits for both families.

Power Optimization of 50 GHz ERSFQ Circuits

The Energy-efficient Rapid Single Flux Quantum (ERSFQ) logic family offers zero-static power dissipation. Any ERSFQ circuit requires a feeding Josephson transmission line (FJTL), a relatively large active transmission line, which serves as an accurate voltage source. For proper operation, the FJTL needs to be continuously pumped at a frequency that is equal to or higher than the highest clock frequency of the ERSFQ circuit. We selected an on-chip pseudo-random binary sequence (PRBS) generator as the example circuit since it naturally facilitates quantitative measurements of operating bias margins in terms of bit error rate (BER). Using external and internal flux pump sources, we performed extensive experimental studies on BER for ERSFQ PRBS generators operating at clock frequencies up to 50 GHz. We paid special attention to the over-pumping regime, where the FJTL pump frequency is higher than the PRBS clock frequency and confirmed its superiority in improving BER. At 35.56 GHz clock frequency, a group of 4 PRBS generators and 4 individual FJTLs with the bias current ratio (BCR) equal to 1, had a BER lower than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> and bias margins of ±25% for internal and external flux pump sources over-pumping at 6.25% above clock frequency. The maximal operational clock frequency of a single ERSFQ PRBS generator with intrinsic pump source (+6.25% over-pumping) and BER <10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> was 49.53 GHz. We also focused on optimization of the FJTL's size to reduce the power consumption and the area occupied by the FJTL itself. All chips were fabricated at MIT-Lincoln Laboratory using the SFQ5ee fab node. Future steps required for better understanding of ERSFQ operation are discussed.